1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which operates in synchronization with a rise and fall of an external clock and which includes a clock generating circuit generating an internal clock in synchronization with the external clock.
2. Description of the Background Art
In a synchronous dynamic random access memory (hereinafter, referred to as SDRAM) operating in synchronization with an external clock supplied externally, a clock generating circuit is installed inside SDRAM and an internal clock in synchronization with the external clock is generated in the clock generating circuit to perform an input-output operation of data using the internal clock. Therefore, an input-output timing of data is largely affected by a phase accuracy of the internal clock thereon.
In recent years, by the demand for a higher frequency operation of a semiconductor memory device, development has been made and put into practical use, of a double data rate SDRAM (hereinafter, referred to as DDR SDRAM) in which inputting and outputting of data are performed in synchronization with a rising edge and falling edge, respectively, of an external clock.
In this DDR SDRAM, a phase difference between an edge of an external clock and an input-output timing of data of the DDR SDRAM is required to be smaller than in a case of a general SDRAM in which inputting and outputting of data are performed in synchronization with only a rising edge of the external clock. That is, this is because, since the DDR SDRAM performs data inputting-outputting at a frequency twice as high as that of the general SDRAM, a drift in phase between an edge of the external clock and a data input-output timing becomes larger relative to a cycle of the external clock.
FIG. 39 is an operating waveform diagram of main signals when data is read from a conventional DDR SDRAM of the first generation type, which is a so-called DDR-I. In the DDR SDRAM shown in the operating waveform diagram, a CAS latency CL is set to 1.5 and a burst length is set to 4. A CAS latency here expresses the number of cycles for the DDR SDRAM to receive a READ command (a command for reading data) externally and then to start to output data to outside, wherein an interval from a rise of external clock EXTCLK till the next rise thereof is one cycle. Note that a burst length expresses the number of bits read out consecutively according to a READ command.
Referring to FIG. 39, the DDR SDRAM outputs a data strobe signal DQS and a data DQ, which is read data, in synchronization with external clocks EXTCLK and EXT/CLK. External clock EXT/CLK is a clock signal complementary to external clock EXTCLK. Furthermore, data strobe signal DQS is a signal coinciding with or in synchronization with a timing edge of data DQ outputted to outside.
A timing difference tAC between an edge of external clocks EXTCLK, EXT/CLK and an output of data DQ is defined so as to be confined in a prescribed range, and in FIG. 39, a timing difference tAC is controlled to be 0. Furthermore, a difference tDQSQ in output timing between data strobe signal DQS and data DQ is also required so as to be confined in a prescribed range.
Furthermore, in DDR-I, data strobe signal DQS in reading data is defined to be generated (CAS latency CL-1) cycle before data DQ starts to be output. This period is called “preamble”. In a period of a half cycle after the final data of data DQ starts to be output, data strobe signal DQS is defined so as to be kept at L level (logic low). This period is called “postamble”.
In order to realize data output timings as shown in FIG. 39, an internal clock with a timing slightly earlier than a timing of an edge of external clock EXTCLK becomes necessary in a data output circuit outputting data DQ finally to outside. This is because a delay generates in a period after an external clock is inputted to a semiconductor memory device till data is actually outputted, because of capacitance of internal circuits in the semiconductor memory device.
That is, a necessity arises for a clock generating circuit, generating internal clocks CLK_P and CLK_N shifted backward by an adequate amount of time Ta with respect to an edge of external clock EXTCLK by delaying external clock EXTCLK by an adequate delay amount Tdll, since external clock EXTCLK is a signal with a constant cycle, and capable of controlling the delay amount Tdll so that data DQ and data strobe signal DQS outputted from the data output circuit and a data strobe signal output circuit operating using internal clocks CLK_P and CLK_N as triggers satisfy the above timing differences tAC and tDQSQ. A circuit generating such internal clocks is referred to as a DLL (delay locked loop) circuit.
Backward amount Ta is determined by a propagation time after read data is taken in the data output circuit using internal clocks CLK_P and CLK_N as triggers till the read data is read out finally to a data output terminal. Then, as shown in FIG. 39, in a case where a CAS latency is 1.5, the first data of data DQ is outputted in synchronization with a rising edge of EXT/CLK (a falling edge of EXTCLK) and thereafter, odd-numbered data of data DQ is outputted using internal clock CLK_N as a trigger and even-numbered data is outputted using internal clock CLK_P as a trigger, thus sequentially outputting odd-numbered data and even-numbered data to outside.
FIG. 40 is a functional block diagram conceptually describing a READ-related circuitry operating by internal clocks generated by the DLL circuit.
Referring to FIG. 40, a DLL circuit 1100 receives external clocks EXTCLK and EXT/CLK to generate and output DLL clocks CLK_PF and CLK_NF obtained by delaying respective external clocks EXTCLK and EXT/CLK. A repeater 1150 receives DLL clocks CLK_PF and CLK_NF outputted from DLL circuit 1100 to output respective corresponding DLL clocks CLK_P and CLK_N.
A plurality of data output circuits 1200 are provided based on a word organization to which the DDR SDRAM corresponds. Each of data output circuits 1200 receives DLL clock CLK_P and CLK_N outputted from repeater 1150, and takes in data read out onto data bus from a memory cell array to output. In a case of DDR-I, reading data from the memory cell array every one cycle is an operation in 2-bit prefetch in which 2 bit data is read out to each data output circuit in one reading. That is, in each data output circuit 1200, 2 bit data is simultaneously read from the memory cell array in each cycle and the 2 bit data is in a set order transferred in each half cycle to be outputted to outside.
Here, it is common that signal paths to data output circuits 1200 from DLL circuit 1100 is of a tree structure, and the circuits and signal lines are arranged so that the data output timing is not different largely among a plurality of data output circuits 1200. Repeaters 1150 are usually provided on the basis of one repeater 1150 to 8 or 4 data output circuits.
Data strobe signal output circuit 1500 generates and outputs, to outside, data strobe signals LDQS and UDQS indicating timings at which data is outputted from data output circuits 1200 to outside. Data strobe signal output circuit 1500 receives DLL clocks CLK_P and CLK_N outputted from repeater 1150, generates data strobe signals LDQS and UDQS in synchronization with DLL clocks CLK_P and CLK_N during a period from the “preamble” till the “postamble” using a signal QSOE received from a READ control circuit 1400, and outputs thus generated data strobe signal LDQS and UDQS to outside. Here, signal QSOE is a signal for determining an active period of column-related circuits based on burst length BL, in which signal QSOE stays at H (logic high) level during a (a burst length BL/2) cycle after receiving READ command.
READ control circuit 1400 operates in synchronization with internal clock CLK received from a clock buffer not shown, generates various kinds of signals necessary for a data read operation according to READ command, and outputs the signals to data output circuit 1200 and data strobe output circuit 1500.
In company with a trend of down-sizing and low power consumption of electronic equipment in recent years, a requirement for lower power consumption in a semiconductor memory device mounted on the electronic equipment has become severer. In the DDR SDRAM, as a technology for use in realization of lower power consumption, a method is disclosed in Japanese Patent Laying-Open No. 2001-126474 in which reduction of power consumption is realized by improving a synchronous characteristic of output phase.
As shown in FIG. 40, since DLL clocks CLK_P and CLK_N are supplied to various circuits, current consumed by charge and discharge of parasitic capacitance on signal lines, the operations of the various circuits receiving DLL clock and the like amounts to as high a value as several mA. While a proportion of the current related to DLL clock relative to the entire current is low during a period of data reading, the entire current amounts to a value of the order of 20 mA in a standby state where row-related operations are active but none of column-related operations is performed (this state is also referred to as an active standby) and a proportion of the current related to DLL clock relative to the entire currents is very large.
Here, it is possible to reduce the current related to above described DLL clock by activating a circuit at an output stage of DLL circuit 1100 when READ command is received and outputting neither of DLL clocks CLK_PF and CLK_NF except for during data read operation.
However, since the time in which DLL clocks are transmitted to various circuits after READ command is received is constant, it is hard to stably supply DLL clocks to the various circuits before data output is started when CAS latency is short or when the operation frequency is high. Especially, as described above, a necessity arises for providing a “preamble” in one cycle prior to data output in data strobe signal DQS, and DLL clock needs to be supplied to data strobe signal output circuit 1500 at an earlier timing.
Referring again to FIG. 39, when CAS latency CL is 1.5, a circuit at an output stage of DLL circuit 1100 is necessary to be activated so as to be in time for DLL clock CLK_NF corresponding to the first DLL clock CLK_N after READ command is received in order to start the “preamble” in synchronization with external clocks EXTCLK and EXT/CLK 0.5 cycle after READ command is received. In reality, it is desirable that before signal QSOE, which is an original signal of data strobe signal DQS, is outputted to data strobe signal output circuit 1500 from READ control circuit 1400, a circuit at an output stage of DLL circuit 1100 is activated, and DLL clock CLK_NF corresponding to the first DLL clock CLK_N after above described READ command is received is outputted from DLL circuit 1100.
In the following description, consideration will be given to an operating frequency of a DDR SDRAM satisfying the conditions. Circuits in the DDR SDRAM operate in synchronization with internal clock CLK outputted from a clock buffer taking in external clocks EXTCLK and EXT/CLK thereinto except for a case where DLL clock CLK_P and CLK_N are used in order to acquire data input-output timing.
If a time after READ control circuit 1400 receives internal clock CLK till outputting signal QSOE is Tda, a cycle of external clocks EXTCLK and EXT/CLK is Tck, a delay time of internal clock CLK behind external clocks EXTCLK and RXT/CLK is Tdc and a propagation time of a signal from DLL circuit 1100 to data output circuit 1200 is Tdp by definition, a necessity arises for establishing the following equation in order to satisfy the above conditions.Tdc+Tda<Tck/2−(Ta+Tdp)  (1)
Here, time Ta is a backward amount of DLL clocks CLK_P and CLK_N relative to above described external clock EXTCLK and EXT/CLK. The left-hand side of the equation (1) is a time till signal QSOE is generated from the external clocks EXTCLK and EXT/CLK at which READ command is received. On the other hand, the right-hand side thereof is a time till the first DLL clock CLK_NF is generated from the external clocks EXTCLK and EXT/CLK at which READ command is received. By rearranging the equation (1) with respect to cycle Tck, the following equation is obtained:Tck>2×((Tdc+Tda)+(Ta+Tdp))  (2)
That is, the equation (2) means that when an operating cycle is equal to or less than a time shown by the right-hand side, in other words, in a case of being equal to or higher than an operating frequency, generation of the “preamble” of data strobe signal DQS is short of time even if a circuit at an output stage of DLL circuit 1100 is activated after READ command is received, which means disabling of proper output control.
In a case where in a conventional DDR SDRAM, CAS latency CL is set to 1.5, an operation is set in advance so that transmission control of DLL clocks is not performed by READ command when being used in a high frequency or in a case where an operating margin is not sufficient. In such a case, DLL clocks is commonly controlled in transmission based on ACT command activating row-related operations.
While the “preamble” output of data strobe signal DQS is guaranteed according to transmission control of DLL clock with ACT command, transmission control of DLL clock according to READ command is not performed during the use at a frequency satisfying the equation (1), therefore disabling reduction in currents in the active standby.
Furthermore, backward amount Ta and times Tda and Tdc are changed by operating environment such as an environmental temperature and external/internal voltages. As can be understood from the equation (1), an operating frequency satisfying the conditions changes according to an environment in which DDR SDRAM is actually used. That is, even when an operation is set so that transmission control of DLL clock is enabled according to ACT command based on a preliminary study, a case can also be arisen where the equation (1) is sufficiently satisfied in an actually used environment. A conventional DDR SDRAM, however, was not able to be adapted to such fluctuations in operating environment.